A 12-bit 10MS/s 2-stage algorithmic ADC in 130-nm CMOS utilizing capacitor sharing and capacitor scaling technique

This paper presents a low power 12-bit 10MS/s algorithmic analog-to-digital converter (ADC) implemented in a 130-nm CMOS technology. A technique is proposed for using capacitor scaling and capacitor sharing to reduce the power requirements of algorithmic analog-to-digital converters. The ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 66dB while consuming 1mW from a 1.5V supply.