A high power and high efficiency GaAs BPLDD SAGFET with WSi/W double-layer gate for mobile communication systems

A buried p-layer LDD (BPLDD) self-aligned gate FET (SAGFET) with a WSi/W double-layer gate for high power amplifiers operating at low voltage supply has been successfully developed. This FET has delivered the high breakdown voltage due to the offset gate structure and the n'- layer separation from the gate edge by sidewall assisted ion-implantation technology. A WSi/W double layer gate structure was employed to reduce the gate resistance. The 1 /spl mu/m gate-length, 1.2 mm gate-width FET exhibited an output power of 24.7 dBm, a power-added efficiency of 54%, and an adjacent channel leakage power of less than -55 dBc at a 1 dB compression power of 22 dBm under a drain bias of 3.3 V at 1.9 GHz.