DC characteristics of Junction Vertical Slit Field-Effect Transistor (JVeSFET)

This paper presents a simulation based feasibility study of deep-submicron JFETs obeying an extreme layout regularity, that is a foundation of a new vertical slit geometry ICs (VeSTICs) vision proposed in. DC characteristics obtained for symmetrical dual gate JVeSFETs have been investigated in a wide range of bias voltages. As a conclusion an assessment of applicability of these devices in nano-size era SoCs is proposed.