Novel circuit solutions for rail-to-rail CMOS buffer

The design of low-power rail-to-rail output buffers for high capacitive loads is critical. In particular, control of the output current, constant input transconductance and output stage driving must be well confined. In this paper we discuss the major design constraints and present a new topology for a CMOS rail-to-rail output buffer. The experimental results show that the proposed architecture is suitable for input-output signals within the full dynamic.