Compact Model of Carbon Nanotube Transistor and Interconnect

A noniterative physics-based compact model is developed for carbon nanotube (CNT) transistor and interconnect in order to support early stage design exploration. Based on the derivation of surface potential, the new model accurately predicts both $I$– $V$ and $C$– $V$ characteristics. It is scalable to key process and design parameters, such as the diameter, chirality, contact materials, gate dielectrics, and bias voltages. Without any iteration in model computation, the proposed model significantly enhances the simulation efficiency for large-scale design research. By benchmarking circuit performance, the optimal space of the CNT process is further localized. It is observed that for a Schottky-barrier CNT transistor with the diameter range of 1–1.5 nm, the circuit can be more than 8$\times$ faster than that of 22-nm CMOS, with the tolerance to the variation in contact materials.