Transistor Pulse Circuits for 160-MC Clock Rates

This paper consists of two parts. Part I, by Giguere and Jamison, discusses transistor circuits capable of regenerating 6.25-mμsec pulses at a 160-mc bit rate. Part II, by Noll, discusses techniques for multiplexing 16 digital signals with a 10-mc clock rate into a single signal with a 160-mc clock rate. Two methods of performing the regeneration function are presented. One method consists of dc level restoration for recognition of the signal and constant current coincident circuitry for the reconstruction of the pulses. The second method consists of operating on changes in the signal for pulse recognition and the use of a bistable circuit for pulse reconstruction. Timing in the second case is obtained by a constant current coincidence gate. Parallel-to-serial multiplexing techniques have been developed to combine sixteen parallel 10-mc clock-rate signals into a 160-mc clock-rate pulse train. The sixteen synchronous signals are applied to sixteen AND gates along with a 10-mc narrow gate pulse. The space separations of the resulting regenerated and timed AND gate output pulses is converted to time separation with only a small amount of signal loss. This is done by injecting the pulses at sixteen equally separated points on a broad-band delay line. Methods have been developed to reduce spurious responses resulting from multiple reflections on the delay line. The current mode transistor AND gates are suitable for AND/OR functions for individual 4-mμsec logic. The multiplexer may also be used as a piece of test equipment to generate repetitive 16-bit binary.