Static CMOS latch-up considerations in HVIC design

Static latchup in CMOS devices placed on a thin epitaxial layer for high-voltage integrated circuits (HVIC) is investigated using SPICE. The layout configuration and substrate current have a major influence on CMOS latchup as compared with conventional CMOS structures. Special latchup conditions exist for NMOS devices adjacent to high-voltage devices due to an extra p-n-p-n path. The results suggest that the use of PMOS adjacent to the high-voltage is best suited, in terms of layout, to avoiding latchup conditions. It is also shown that the latchup of CMOS devices is improved by placing them in an n/sup -/ epitaxial layer on a p/sup -/ substrate.<
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