Pseudo-random behavioral ATPG

This paper deals with a new approach for the Automatic Test Pattern Generation (ATPG) of circuits described from a behavioral point of view in VHDL. This approach is based on a pseudo-random process characterized by the fact that criteria for computing the test length and evaluating the quality of the generated data come from the field of software engineering. This paper presents the bases of this new approach in the field of hardware engineering and some experimental results.