Testability of floating gate defects in sequential circuits

The logic detectability conditions of floating gate (FG) defects in sequential circuits are considered. It has been found that a FG defective sequential circuit may be able to memorize one or two logic states depending on the values of the defect parameters. I/sub DDQ/ testing may detect a large class of floating gate defects including some defective transistors located in logically untestable branches. Good agreement is observed between the theoretical and simulated results with experimental measurements performed on a typical scan path cell designed intentionally with floating gate defects.