The best-case power-delay products for polysilicon-contacted bipolar-transistor gates. A theoretical study

The best-case power-delay products for bipolar-transistor gates that have optimally designed transistors with polysilicon-contacted emitters, both with and without interfacial layers between the polysilicon and underlying emitter, are predicted. It is shown that gates that have one or the other of these contacted-resistors have comparable power-delay products. Because this modeling is very general, it is believed the results are applicable for arsenic as well as phosphorous-doped polysilicon-contacted bipolar transistors.<
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