Co-design of reliable signal and power interconnects in 3D stacked ICs

With the rapid advance of die stacking and through-silicon-via fabrication technologies, the era of 3D ICs is near. Yet, the knowledge base of 3D IC design techniques is still not matured enough. In this paper, we investigate the design issues raised during the system-level integration of signal and power interconnects in 3D ICs. Routing congestion and power noise are analyzed, and various factors that affect performance and reliability metrics are identified.