A second generation charge integrator and encoder ASIC

A second generation charge integrator and encoder ASIC (QIE5) has been designed for the KTeV experiment at Fermilab. It is intended to be used in conjunction with a FADC (typically eight bits) to digitize photomultiplier tube (PMT) current pulses at a fast rate, with variable resolution over a 16 bit dynamic range. QIES integrates pulses of up to 30 ma peak on eight nonoverlapping binary scaled ranges. A system clock of up to 53 MHz controls the integration period and readout rate. The device is pipelined so that there is no signal deadtime. For each clock period, one range is selected depending on the signal magnitude, and the output of that range is routed to the QIES analog output and fed to the FADC to form the mantissa. The selected range is encoded and output as a three bit digital exponent. With this method, the measurement resolution is a relatively constant fraction of the signal over a large dynamic range. Previous reports have described a single ended device (QIE2) which had inherent limitations. The QIES is a fully differential design and contains numerous other features which provide significant performance improvements. The new design philosophy and test results are presented for the first time.