Transparent multi-core cryptographic support on Niagara CMT Processors

How cryptographic functionality has been implemented and made available in application scenarios has evolved over time. Pure software implementations were the obvious first choice, followed by dedicated hardware devices, be it co-processors or hardware accelerators accessible on the main bus. This paper examines aspects of making the next step in this evolution work, namely the use of dedicated cryptographic hardware that's part of multi-core system CPUs. While the inclusion of cryptographic accelerator functionality in the processor chip is not new, this paper investigates the question of how to transparently combine such multi-core cryptographic processor support with higher level software stacks in a commodity operating system that also needs to perform well if such hardware support is not present. We explore this question in the context of the Ultra-SPARC T1 and T2 processor family, chip multi-threaded (CMT) processors that have hardware cryptographic accelerators integrated on-chip with 8-core support for symmetric and asymmetric cryptographic and secure hash operations. The paper presents how a software infrastructure, the Solaris Cryptographic Framework, transparently takes advantage of these chip features and presents a brief comparative study of their performance.