Inversion channel edge in trench-isolated sub-1/4-/spl mu/m MOSFET's

A comprehensive quantitative study of edge effects in the channel of trench isolated sub-1/4-/spl mu/m CMOS devices is presented. Model devices derived from CMOS technologies have been examined using three-dimensional (3-D) finite element device simulation. The off-state, turn-on, and on-state device characteristics of the channel edge and terminal currents and their sensitivity to channel edge geometry, doping, oxide thickness and interface charges have been quantified. Analysis of on-state current shows that edge-effect models should include comparable contributions from decrease in threshold voltage and increase in effective width. The edge effect is shown to interact with the short-channel effect. Methods for minimizing the trench edge effect are quantified including edge doping, channel edge rounding, and recessing the channel below the top of the trench. The placement of a fixed- or floating-potential field plate in the trench is shown to be an effective method for controlling the edge effect below 100-nm channel widths.