Back gated CMOS on SOIAS for dynamic threshold voltage control

Simultaneous reduction of supply and threshold voltages for low power design without suffering performance losses will eventually reach the limit of diminishing returns as static power dissipation becomes a significant portion of the total power equation. In order to meet the opposing requirements of high performance and low power, a dynamic threshold voltage control scheme is needed. A novel SOI technology was developed whereby a back-gate was used to control the threshold voltage of the front-gate; this concept was demonstrated on a selectively scaled CMOS process.