FPGA synthesis for minimum area, delay and power

In this paper, we address the problems of minimizing the area, delay and power during synthesis of field programmable gate arrays (FPGAs). We use Boolean decomposition techniques to minimize the number of configurable logic blocks (CLBs), the depth of the network and the power dissipations. We use OBDDs to represent functions so that our methods can be implemented more effectively. Our mapping algorithm is based on function decomposition which was pioneered by Ashenhurst [1959].