Efficiency of probabilistic testability analysis for soft error effect analysis: A case study

Evaluating the potential functional effects of soft errors (single or multiple bit-flips) in digital circuits becomes a critical design constraint. The usual approaches, based on fault injection techniques, suffer several limitations. New approaches, better suited to large circuits with complex workloads, are therefore suitable. An innovative approach was recently proposed, based on probabilistic testability analysis. This paper compares the presented results with results obtained from extensive fault injection campaigns.