A CMOS 6 b 200 M sample/s 3 V-supply A/D converter for a PRML read channel LSI

There is a strong demand for high speed ADCs for PRML read channel LSI. Most of these ADCs are fabricated with bipolar or BiCMOS, because of high-speed operation. Conventional CMOS ADCs have 100 MSample/s conversion rate and insufficient tolerance to power supply noise. These problems are overcome by interleaved auto-zeroing (IAZ) architecture and output-swing limiting comparator (OLC). The ADCs operate at 200 MSample/s in a mixed PRML read channel LSI.