A 160 MHz front-end IC for EPR-IV PRML magnetic-storage read channels

The analog signal-conditioning front-end described overcomes delay and quantisation noise problems. An analog adaptive (or programmable) filter equalizes the continuous-time waveform, then the first stage in a discrete-time analog delay line samples it at frequency and phase determined by a clock-recovery PLL. With no equalizer delay in the loop, the PLL acquires frequency and phase almost ten times faster than the conventional system. Furthermore, when the maximum-likelihood detector is digital, the fully-conditioned signal may be digitized with only a 5 b ADC, half the hardware complexity of the 6 b flash ADC. This implementation in 1 /spl mu/m CMOS of the signal-conditioning front-end equalizes the read waveform to an EPR-IV target at a 160 MHz sample rate.