n/sup +/-polysilicon gate PMOSFET's with indium doped buried-channels

A n/sup +/-polysilicon gate PMOSFET with indium doped buried-channel is discussed, The gate length scaling of n/sup +/-polysilicon gate buried-length PMOSFET's is limited by the channel punch-through effect. Designing shallow counter-doped layers (buried-channels) has been established as a means to reduce the undesirable short channel effects in these devices. Indium, an acceptor dopant in Si, has a low diffusion coefficient and implant statistics favorable for achieving shallow doping layers. Indium implants are explored (as an alternative to BF
₂
) to counter dope the n-tub for adjusting the threshold voltage. Devices are fabricated using AT&T's 0.5 μm CMOS technology but with t/sub ox/=50 /spl Aring/. Although no special effort has been made to optimize the n-tub or to take full advantage of the diffusion and implant characteristics of indium, excellent electrical results are obtained for devices with L/sub eff/=0.25 μm. Improved V/sub th/ roll-off characteristics and reduced body effect (/spl gamma//spl ap/0.18 V
¹
2 / versus /spl gamma//sub B//spl ap/0.40 V
¹
2 /) in indium implanted buried channels are demonstrated over BF
₂
implanted buried channels for PMOSFET's with identical long channel threshold voltages. The effects of incomplete ionization (freeze-out) of the indium acceptor states on the electrical device characteristics are demonstrated by device simulations and measurements.