Design and implementation of pipelined DRR ASIC

In this paper, a novel scheme called Pipelined Deficit Round Robin (PDRR) is proposed for packet scheduler. We reorder the processing stages and use the pipelined method to reduce the delay time. The scheme preserves O(1) complexity in hardware. By the simulation result, PDRR has 60% improvement better delay time than DRR. The ASIC operates approximately 3.5ns by 0.18 um CMOS technology and supplied with 1.8V and power dissipation is 47 mW. The area is 0.845 mm X 0.879 mm involving pads. It can furnish approximately 285.71 MHz so that is enough to satisfy OC-768.