Low-voltage analog IC design in CMOS technology

In this brief, various problems confronting analog designers due to low supply voltage requirements are investigated. Some of the limiting factors are determined, and new solutions for low voltage design are proposed and demonstrated in two different circuits, namely a linear four quadrant analog multiplier and a rail-to-rail constant-g/sub m/ input stage. The circuits were fabricated in a p-well 2 /spl mu/m CMOS process available through MOSIS.