A transistor-based background self-calibration for reducing PVT sensitivity with a design example of an adaptive bandwidth PLL

A transistor-based background on-chip self-calibration technique is proposed to obtain PVT-independent circuit parameters. With little implementation complexity, the proposed direct I-V calibration of performance determining transistors efficiently achieves stable operation of precision circuits. As an example application to a design of a PLL, the calibration scheme adjusts critical parameters such as VCO gain and charge-pump current to achieve adaptive bandwidth characteristics. The PLL, implemented in a 0.18μm CMOS, shows a wide lock-range of 10Mhz–1Ghz with the rms jitter of 5.7ps at 1Ghz.