Solving issues of integrated circuits by 3D-stacking meeting with the era of power, integrity attackers and NRE explosion and a bit of future

In the foreseeable future, VLSI design will meet a couple of explosions: explosion of power, explosion of integrity attackers including power integrity and signal integrity and explosion of NRE (non-recurring engineering cost). A remedy for power explosion and explosion of integrity attackers lies in “voltage engineering”. A remedy for the NRE explosion is to reduce the number of developments and sell tens of millions of chips with a fixed design. 3D-stacked LSI approach may embody such possibility. The talk will cover example of the solutions based on 3D-stacking. Several new circuit technologies for voltage engineering, including distributed DCDC converters and proximity interfaces are described to enable 3-D stacking of chips to build high-performance yet low-power electronics systems. On the other extreme of the silicon VLSI’s which stay as small as a centimeter square, a new domain of electronics called large-area integrated circuit as large as meters is waiting to open up a new continent of applications in the era of ubiquitous electronics. One of the implementations of the large-area electronics is based on organic transistors. The talk will provide perspectives of the organic circuit design taking E-skin, sheet-type scanner, Braille display and wireless power transmission and communication sheet as examples.