Parallel Implementation of DPCM Decoding for SMP Systems

DPCM (differential pulse code modulation) coding is widely used in many applications including lossless JPEG compression. DPCM decoding is inherently a 1-indexed or 2-indexed recurrence relation. Thus, although it is hard to parallelize efficiently, some (N log N)or (log
²
N) algorithms have been studied for an N times N image with N times N or N processors. Recently commodity microprocessors are equipped with plural cores and SMP architectures are utilized in some PCs, but the number of parallelism is not so large (up to 80). Thus, it is unrealistic that the image processing of an N times N image is parallelized with N times N or N processors. In this paper, we implements two parallel DPCM algorithms for an N times N image on P processors (P << N): Fat-pipeline and P-scheme. Our experimental results show that both approaches provide the parallelisms of about 3.2 with 6 processing cores.