Evaluation of multiple supply and threshold voltages for low-power FinFET circuit synthesis

In modern circuits, power efficiency is a central determinant of circuit efficiency. The exponential increase in the number of transistors in a chip has led to increased chip power dissipation. Therefore, low-power circuits have become a top priority in modern VLSI design. With scaling, leakage power accounts for an increasingly larger portion (>40%) of the total power consumption in deep submicron technologies. FinFET technology has been proposed as a promising alternative to deep submicron bulk CMOS technology, because of its better scalability, short-channel characteristics, ability to suppress leakage current, and mitigate device-to-device variability when compared to bulk CMOS. The subthreshold slope of a FinFET is approximately 60 mV which is close to ideal. In this paper, we propose a methodology for low-power FinFET based circuit synthesis. A mechanism called TCMS (threshold control through multiple supply voltages) was previously proposed for improving the power efficiency of FinFET based global interconnects. We propose a significant generalization of TCMS to the design of any logic circuit. This scheme represents a significant divergence from the conventional multiple-supply voltage schemes considered in the past. It also obviates the need for voltage level-converters. We employ accurate delay and power estimates using table look-up methods based on HSPICE simulations for supply voltage and threshold voltage optimization. Experimental results demonstrate that TCMS can provide power savings of 67.6% and device area savings of 65.2% under relaxed delay constraints.