CMOS VLSI single event transient characterization

The MOSIS VLSI IC process has been characterized for picosecond single-event transients for large-area diode test structures. Three test structures were designed for a CMOS, p-well, 3- mu m process, including two MOS diodes for SEU transient measurements. Devices were irradiated with 5-MeV boron ions and 5-MeV alpha -particles. Bulk CMOS single-event transients are found to exhibit a wide variety of electrical interactions when the devices are irradiated, owing to complex technology profiles and multijunction effects. The transients characterized in this work can be used to simulate single-event upsets in SRAM (static RAM) circuits.<
>