3-Dimensional Gate Array with Vertically Stacked Dual SOI/CMOS Structure Fabricated by Beam Recrystallization

A three-dimensional(3-D)integration developed by a practical silicon-on-insulator(SOI) technology may offer the great possibility of fabricating even denser very large-scale integration, based on the realization that the present two-dimensional integration will reach its limit of packing density in the near future. Among others, SOI/CMOS integrations are the most promising application of 3-D technology because of their low-power, high-speed functions as well as high packing density. High packing density can be obtained by the simplicity of device isolation and high-operating speed stems from the reduction in parasitic capacitance. Before, we have reported the first successful fabrication of 3-0 CMOS integration by using beam recrystallization with a structure, in which a transistor is fabricated in the recrystallized SOI directly above another transistor in the bulk silicon with separate gates and an insulator in between(1,2).