A New Trench Isolation Technique for MOS VLSI

The LOCOS technique is widely used for LSI isolations. However, if it is used for submicron VLSI, it has the following problems. (1) Large pattern transfer difference between mask layout dimension and final device geometry (bird's beak) and (2) narrow channel effect due to the lateral diffusion layer of channel stop boron. Several submicron isolation techniques, such as SWAMI1) and BOX2), have been proposed. However, they still require the channel stop boron implant to the isolation region sidewall in order to suppress "kink" effect3). This "kink" effect, which is observed in subthreshold current curves in N-MOSFETs with such isolation structures, is caused by high gate field concentration at a sharp corner of the active-to-field-region boundary3). This channel stop boron layer causes the narrow channel effect for a submicron channel width MOSFET. Several "trench" isolation techniques have also been proposed and applied to bipolar4)'5) or CMOS 6) ICs. However, since the purpose of these techniques is to make deep isolation regions, no narrow trench isolation has been tried so far. Ofcource, the feasibility of the trench isolation technique has not been examined using MOSVLSIs.