Multilevel Metallization Technology for VLSIs

Tremendous and continuous increase in packing density and integration scale in VLSIs requires three or four level, fine line ( - 2 μm) metallization E1-4]. Multilevel metallization is not only necessary for increasing interconnect capacity, but is also attractive as an approach to reducing interconnect resistance and capacitance. Multilevel metallization technology, however, involves a variety of problems in almost all VLSI technology fields; layout design C automatic layout and routing ), circuit design ( prediction of and reduction in interconnect resistance and capacitance ), process and materials technologies.