A High Latch-Up Immunity Full CMOS RAM

CMOS has become the main device technology in static RAMs for its low power performance, and a considerable amount of 64K bit CMOS RAMs are now in production. All of them, however, are mixed structure composed of NMOS array and CMOS peripheral. Full CMOS RAM is not in production yet, probably because full CMOS RAM has been suffering a low chip yield and latch-up problem. In order to solve the latch-up problem, many techniques have been proposed, such as a silicon- on- insulator structure, the use of epitaxial wafer and a retrograde well structure. The problem will be more serious as physical dimension is scaled down in VLSI CMOS RAMs. The techniques mentioned above result in a higher cost or lower yield, and are not practical to be applied to the production. This paper will propose a practical solution for the CMOS latch-up problem by improving power supply configuration in the memory cell.