1.25 μm Mosi2/Poly Gate CMOS-SOS Isoplanar Technology

In this paper we describe a 1.25 μm MoSi2/Poly Gate, Self-Aligned Isoplanar, CMOS-SOS Technology. MoSi2/polysilicon gate electrode improves conductivity from 80 Ω/O for P+-poly and 40 Ω/◻ for N+-poly to < 10 Ω/O for the polycide structure. The critical patterns in this process are defined by projection printing and dry etching. The dry etching techniques employed are parallel-plate plasma etching and ion milling. All doping is accomplished by ion implantation. The crossover oxide is a reflowed phosphosilicate glass for improved step coverage, and the metallization is an Al-Si (1% silicon) alloy. Circuits operating at over 400 MHz have been built with this process.