Submicron 3D Surface-Orientation-Optimized CMOS Technology

For achieving high performance VLSI's in logic and memory applications, CMOS becomes the dominant technology due to its high speed operation and low power dissipation. However, since (100) wafer is used from a view point of NMOSFET's characteristics, conventional planar technologies give rise to loss of balance between electron and hole mobility. This unbalance results in large PMOS device size for designing optimum circuits, which naturally increases parasitic capacitances such as junction capacitance and gate capacitance. As a result, obtained CMOS operation speed is lower than expected. (110) Si surface is thus more preferable for PMOSFET's due to the highest hole mobility. However, it degrades NMOS reliability, which is highest on (100) surface orientation [1]. Therefore, it is most desirable to utilize optimum Si surface orientation for NMOSFET's and PMOSFET's individually on the same substrate.