A Manufacturable Selective Tungsten Process for Applications in VLSI CMOS Devices

It is widely recognized that a serious limit on VLSI circuit performance is imposed by the interconnect. As interconnect resistance does not scale "properly" with reductions in geometry, an increasing proportion of the total propagation delay is due to the interconnect, 1 Two critical components of interconnect resistance which must be addressed are the intrinsic resistance of the gate level metallization and the contact resistance of the subsequent layers of metal to heavily doped silicon. Selectively deposited tungsten as a polysilicon shunt or contact barrier will reduce the interconnect resistance. It is the purpose of this work to establish that selective tungsten provides a viable, manufacturable solution to the problems of VLSI interconnect.