Zero Static Power Fuse Circuit

A compact digital fuse circuit that consumes zero static power and forces zero bias across blown fuse links suitable for deep submicron technologies is described. No bias or power-down control signals are required in this fuse concept making it ideal for low power applications. The fuse circuit exploits the availability of system reset signal (power-up, hardware) to sense and latch fuse state data and incorporates fuse isolate capability needed for zero bias. This can be combined with additional logic to offer software programmable functionality in a modular fashion. An inherent feature of the circuit is that the fuse state is valid during the sense phase which is required in power-on-reset (POR) fusing applications. Such fuse circuits have been successfully implemented in 180 nm CMOS technology for use as generic fuses (hard/soft) as well as fusing for power-on/voltage-detect circuit (POR/UVD). A 1.8V supply fusebank circuit comprising 30 hard fuses and 10 soft-fuses occupies an area of 0.04 mm
²
. A 3.3 V supply fusebank circuit comprising 10 soft fuses and 3.3/1.8V level shifters occupies an area of 0.015 mm
²
.