Overmolded flip chip packaging solution for large die FPGA with 65nm low-k dielectrics

Flip chip ball grid array (FGBGA) packaging is widely used for high performance devices that require high pin count and enhanced electrical performance. However, current standard flip chip package construction has difficulties in meeting package coplanarity requirements for large packages, especially with thin core substrates. Moreover, due to concerns with corrosion of exposed passive components, standard flip chip package construction with lid is not suitable for applications in which harsh cleaning solvents are used during board assembly. The utilization of low-k in the silicon to enhance device performance presents additional challenges to component reliability. In order to address these concerns, a molded FCBGA package was developed for large die (∼23 mm
²
) devices. In the molded flip chip package, the die is underfilled as well as overmolded. This overmolded structure provides good package coplanarity, protection from harsh environments, and structural support for thin substrates. It also offers good bump protection and improves board level reliability. During this study, three different mold compounds were tested with 65nm and 90nm low-k test vehicles with die sizes greater than 21 mm. Effect of different factors such as substrate solder mask, die size, and molding compound properties on the assembly and reliability was studied during these evaluations. This paper also discusses other assembly process related factors that can impact the reliability of the molded flip chip package with large low-k die and large packages. The study shows that the molded FCBGA structure improves the warpage of large packages and can provide good reliability performance for large die with low-k dielectrics. These results also indicate that molded flip chip, which employs high modulus mold compound to give low warpage, could be a potential solution for lead free flip chip packages.