"Split-ADC" Digital Background Correction of Open-Loop Residue Amplifier Nonlinearity Errors in a 14b Pipeline ADC

The "Split ADC" architecture concept is applied to correction of errors due to nonlinearity of an open-loop residue amplifier in a pipeline ADC. Determination of calibration parameters and correction of errors takes place entirely in the background in the digital domain; no interaction with analog circuitry is required. An algorithm exhibiting convergence of calibration parameters in fewer than 100 000 conversions is presented.