A 1 Mbit SRAM test structure to analyze local mismatch beyond 5 sigma variation

We present an area efficient test structure that allows a measurement of the statistical distribution of SRAM cell currents beyond 5 sigma variation. The test structure was fabricated in a 90 nm and a 65 nm CMOS technology. The measured data show that the device variations are Gaussian-distributed for more than 1 million devices, covering more than 5 sigma of variation. Monte Carlo simulations are used to validate the measurements.