Design verification techniques for system level testing using ASIC level BIST implementations

Requirements and design verification techniques for system level testing using BIST implementations in ASICs are discussed. A logic simulation technique is presented which determines whether reproducable BIST results can be obtained during system level testing. Using this approach, problems which could lead to nonreproducible BIST results during system level testing can be easily identified and corrected during device level of design,.<
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