A 9GHz 320×80bit Low Leakage Microcode Read Only Memory in 65nm CMOS

This paper describes a 320times80bit microcode ROM for 9GHz operation in 1.2V, 65nm CMOS technology. An extended pre-fabrication technique is proposed, which allows optimal programming of local/global merge circuitry, pre-charge devices, column-select multiplexers, and wordline driver strengths. The proposed technique enables 32% leakage and 15% total array power reduction without any delay or area penalty