Single-chip Integration of SRAM and Non-volatile Memory using Bit-line Sharing

A new memory architecture integrating SRAM and Flash within the same array is presented and demonstrated in a standard 0.25mum CMOS process with a memory access time of 20ns. Differential pair Flash cells with low programming current share the same bit-lines as SRAM cells within the same array. This enables row-to-row transfer of data between Flash and SRAM cells as well as access data through I/O directly, in return improving speed and lowering power. Area is saved through the shared usage of column decoding, sense-amplifier, and write-driver circuitry