A 100 MHz 2-D 8/spl times/8 DCT/IDCT processor for HDTV applications

This paper discusses the design of a combined DCT/IDCT CMOS integrated circuit for real time processing of HDTV signals. The processor operates on 8/spl times/8 blocks. Inputs include the blocked pixels that are scanned one pixel at a time, and external control signals that control the forward or inverse modes of operation. Input pixels have a precision of 9-b for the DCT and 12-b for the IDCT. The layout has been generated with a 0.8 /spl mu/m CMOS library using the Mentor Graphics GDT tools and measures under 10 mm/sup 2/. Critical path simulation indicates a maximum input sample rate of 100 MHz.<
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