A reconfigurable ASIC front end

This paper describes the work carried out on developing a reconfigurable ASIC front end for an intelligent sensor system. It is part of a joint industrial and academic research programme in ASICs for smart sensors involving the University of Southampton, Lucas Advanced Engineering Centre and European Silicon Structures (ES2). A test chip has been produced which facilitates the investigation of various aspects of system reconfiguration under digital control. In order to maximise the capability for experimentation, there is a high pin count so that interconnections and resistors can be added externally. The device is realised as standard CMOS library subsystems within the ES2 process. Ten-bit analogue-to-digital conversion (ADC) and digital-to-analogue (DAC) conversion are included.<
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