Conceptual Hierarchical Image Processor (CHIP), an architecture for real-time machine vision

The Conceptual Hierarchical Image Processor (CHIP) is an architecture for real time image processing (IP) applications. It combines a transputer array with a collection of low level processing modules, interconnected using a reconfigurable crossbar switch to provide appropriate processing support for both low-level and high-level IP operations. The architecture is flexible and expandable, in that new low-level modules can be added to the architecture as required by each application. CHIP is designed to be a test-bed for new IP algorithms and new processing module architectures. IP applications can be developed on the CHIP system, and the required low-level and high-level processing resources can be identified. New low-level modules may be prototyped very simply, using commercial off-the-shelf (COTS) devices where available. Once the algorithm and the necessary hardware have been developed and proved, a final target version may then be constructed. This will typically be much simpler than the CHIP, since it will not require the same level of flexibility or reconfigurability. The target may be implemented in an alternative technology, for example, by using ASICs for the processing modules, to meet any size constraints (for example, in airborne or hand-held systems).<
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