A 500 kHz 14-bit BiCMOS ADC

This paper presents the design of a flexible 500 kHz 14-bit ADC for manufacture with 2 mu m BiCMOS technology and optimised for use in multiplexed applications. The paper begins by outlining the ADC application and goes on to provide an account of the algorithm, architecture and block-level implementation. The design is based on the classic two-pass residue algorithm, but uses digital signal processing of multiple second-pass samples to allow 14-bit conversion (with two bits of overlap) using only two 7-bit flash ADC's. The advantages of the technique are significant savings in silicon area and the ability to trade conversion rate for signal-to-noise ratio. Both analogue and digital functions are implemented using differential current-mode circuit techniques to enhance rejection of, and reduce generation of, power supply noise. This is of particular importance in residue algorithm converters, where sensitive analogue circuits must co-exist with fast digital logic. In order to allow a thorough evaluation of the major circuit blocks, the prototype monolithic system has been implemented, initially, as a two-chip set.<
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