An engineering model for short-channel MOS devices

An engineering model for short-channel MOS devices which includes the effect of carrier drift velocity saturation is described. Based on a piecewise carrier drift velocity model, simplified expressions for the DC drain current I/sub D/, the small signal transconductance g/sub m/ and the output conductance g/sub ds/ in the saturation region are derived. For a given gate voltage, the expressions depend only on the threshold voltage V/sub T/ and the dimensions of the device, whose desired values are normally known.<
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