A pass transistor design methodology for 256 Mbit DRAM and beyond

A novel pass transistor design methodology to optimize gate oxide thickness (t/sub ox/), booted wordline voltage (V/sub WL/), substrate bias (V/sub sub/), and processing conditions is presented in this paper. It is found that for a gate length of 0.3 /spl mu/m a t/sub ox/ of about 85 /spl Aring/ (which is much thicker than the /spl sim/65 /spl Aring/ t/sub ox/ for 0.25 /spl mu/m logic technology) to support a V/sub WL/ of 3.75 V, a V/sub sub/ of about -1 V, and As LDD are the optimum technological choices for 256 Mbit DRAM.<
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