Scaling of tunnel oxide thickness for flash EEPROMs realizing stress-induced leakage current reduction

It has been reported that the tunnel oxide of flash E/sup 2/PROM is spoiled by the write/erase sequence of high-field stress and that leakage current (J/sub leak/)is induced at lower voltage, which deteriorates retention time and limits the tunnel oxide thickness of E/sup 2/PROM/sup ./ In order to scale down the tunnel oxide thickness, this paper proposes two new approaches to decrease the leakage current. One is the decreasing impurity concentration in the floating gate poly-Si. The other is to lower annealing process temperature after the floating gate formation. These reduction of J/sub leak/ is more remarkable as the tunnel oxide thickness is thinner. As a result, the tunnel oxide can be scaled down to 6 nm by decreasing gate poly-Si concentration to about 5/spl times/10/sup 19/cm/sup -3/ and lowering annealing temperature to less than 900/spl deg/C. These process will become the key technology to realize 64 Mb E/sup 2/PROM and beyond.<
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