Two-dimensional analysis of a merged BiPMOS device

The BiPMOS device associated with n-well BiCMOS technologies consumes a substantial area for isolation. A merged BiPMOS device structure is introduced to reduce the device size for BiCMOS VLSI. The performance of the merged BiPMOS device has been analyzed using PISCES-2B, a program for solving Poisson and continuity equations. Comparisons between the merged BiPMOS device and a conventional one show that the merged BiPMOS device, which occupies a much smaller area, has a comparable performance.<
>