Extraction of defect size distributions in an IC layer using test structure data

This paper demonstrates the need for specialized test structures and algorithms to obtain defect characteristics which are necessary for accurate yield prediction. Using one such specialized test structure, a general methodology for extracting size distribution parameters for both shorts and opens in any IC layer, which is independent of defect and yield models, is developed in this paper. The application of this methodology is illustrated by means of a fabrication experiment.<
>